1. Field of the Invention
The present invention generally relates to the manufacturing of metal-oxide-semiconductor field effect transistors (MOSFETs), and more particularly to FinFETs and other transistors based on an active region perpendicular to the plane of the silicon wafer. Even more specifically, this invention deals with those instances where random variations of the threshold voltages of such transistors adversely affect integrated circuit performance.
2. Prior Art
Transistors built on a silicon fin were demonstrated as early as 1991 (Hisamoto, D., et al., “Impact of the vertical SOI ‘DELTA’ structure on planar device technology,” Electron Devices, IEEE Transactions on, vol. 38, no. 6, pp. 1419-1424, June 1991) with the goal of achieving better transconductance and superior On/Off ratios. The fin structure was identified for its superior short channel performance in the late 1990's (Xuejue Huang, et al., “Sub 50-nm FinFET: PMOS,” Electron Devices Meeting, 1999. IEDM Technical Digest. International, pp. 67-70, December 1999) from which the name FinFET came to represent this class of transistor. The absence of doping ions in FinFETs promised the absence of random variation in threshold voltage (σVT) attributable to random doping fluctuations (Meng-Hsuch Chiang, et al., “Random Dopant Fluctuation in Limited-Width FinFET Technologies,” Electron Devices, IEEE Transactions on, vol. 54, no. 8, pp. 2055-2060, August 2007), but that promise fails when the fin is doped. For traditional planar transistors, several artisans have shown that an epitaxial channel can significantly reduce the threshold variations due to random doping fluctuations. Representative publications include Takeuchi, K., et al., “Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation,” Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, pp. 841-844, December 1997 and Asenov, A., Saini, S., “Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and δ-doped channels,” Electron Devices, IEEE Transactions on, vol. 46, no. 8, pp. 1718-1724, August 1999.
For very small transistors, variations in threshold voltage due to random doping variations are inevitable because the uncertainty in any group of N items, ionized doping ions in this case, is approximately N1/2. For an ensemble of 106 or 108 ions, the N1/2 uncertainty is 103 or 104 respectively, small (<1%) compared to the overall number of doping ions. However, for nanometer scale transistors, the depleted volume is in the range of 5×10−18 cm3. If the doping level is 1019/cm3, the mean number of active dopants is about 50, and the standard deviation in that number is just over 7. That represents an uncertainty of 14%. Modern transistors use high-K gate stacks and gate work function engineering to allow the use of a lightly doped substrate, which reduces the impact of the doping uncertainties. The impact of uncertainty due to variation in the number of dopant atoms continues to pose a challenge because the effect becomes more important as transistors get smaller. As long as FinFET or TriGate transistors are manufactured with fins that are free of doping, they are highly immune to threshold variations arising from the random dopant variations. Work function engineering has made that feasible for some ranges of threshold voltages, but if higher threshold voltages are required, doping the fins becomes necessary. Once the fins are doped, the N doping atoms in the fin determine the threshold voltage, and the threshold variation due to random distribution of the dopant atoms (the N1/2 problem) comes to the fore. The understanding that has come from analysis of planar epitaxial MOSFETs shows that providing separation between the gate-to-channel interface and the ionized charges mitigates the effect of random doping variations, substantially reducing the resulting variations in threshold voltage.
Another vein of activity in planar transistors has been disclosed by Sugihara et al. in U.S. Pat. No. 6,566,734, “Semiconductor device,” and in a different form by Lee in U.S. Pat. No. 6,627,488, “Method for fabricating a semiconductor device using a damascene process.” In certain embodiments, Sugihara prepares a transistor by selectively etching the silicon substrate in the channel region, then growing an epi layer in that recess. The goals of these actions are to provide better control of the channel doping, less intrusion of the lightly doped drain regions into the channel, and stress management. Lee prepares a similar structure using what he describes as a damascene process. Lee addresses problems associated with the plasma etching required for a planar Gate Last process, and he also employs implants in the recess to create a highly retrograde doping profile beneath the active channel. Asenov went beyond the ideas of Sugihara and Lee to incorporate RDD mitigation in a “Channel Last” planar transistor device as described in US 2013/0049140 A1, “Variation Resistant Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).”
FIGS. 1a-1d show schematic representations of four representative classes of three-dimensional transistors, all of which are prior art with respect to this invention. In each case the cross section represents the zone between the source and drain, and beneath the gate, i.e., the active channel. Current flow would be perpendicular to the plane of these diagrams. FIG. 1a shows a TriGate transistor in which the fin 13 contacts the substrate 10, penetrating the isolation oxide 11. The region identified as 13 is the active fin, which may be undoped or doped to a level that sets the appropriate threshold voltage. The active fin 13 is surrounded by a gate dielectric 16, which is typically a high-K gate stack. The gate electrode 17 is normally a metal chosen for its work function, one of the key factors in defining the threshold voltage. Finally, the region 18 represents a deposited layer that provides both electrical contact and mechanical protection for the metal gate 17. Region 18 is typically amorphous silicon. Typical materials for the metal gate include TiN, but many other materials are being used or considered.
FIG. 1b shows a FinFET in which the active fin's cross section 13 resembles a triangle, and it is connected to the substrate 10. This transistor structure is completed by the isolation oxide 11, a high-K gate stack 16, a metal gate 17 and a gate connection 18, typically amorphous silicon.
FIG. 1c shows an alternative TriGate structure, but the fin 13 is fully isolated from the substrate 10 by a buried oxide 12 because this is an SOI TriGate FET. The balance of the structure resembles FIGS. 1a and 1b, with a high-K gate stack 16, a metal gate 17 and a gate contacting layer 18.
FIG. 1d shows a more classical SOI FinFET, with a nitride cap 14 on the fin 13 that assures the conducting channels in the active transistor are confined to the vertical walls of the fin 13. The structure includes the substrate 10, a buried oxide 12, a high-K gate stack 16, a metal gate 17 and a gate contactor 18.